1. Field of the Invention
This invention relates to a data transfer apparatus, more specifically to the data transfer apparatus transferring asynchronously parallel data by handshake system and a pipeline processing apparatus using the data transfer apparatus and in more detail to the data transfer apparatus using static latches to hold data and the pipeline processing apparatus using the data transfer apparatus.
2. Description of the Prior Art
The inventors of this invention have previously proposed a data transfer control circuit in U.S. patent application No. 07/157,194. At first, with reference to FIG. 1 through FIG. 3, first this invention will be described.
FIG. 1 is a block diagram showing the schematic configuration of a pipeline processing apparatus having two-stage configuration as an example.
The pipeline processing apparatus is configured by series-connected handshake transfer control circuits 811, 812 and 813 and by series-connected parallel data latches 821, 822 and 823 with combinational logic circuits 831 and 832 provided between the latches.
Also, each of the combinational logic circuits 831 and 832 is configured by a decode unit and logic unit.
Such pipeline processing apparatus is operated as follows:
When the handshake transfer control circuit 811 is ready to accept data, it outputs an acknowledge signal (hereafter called Ack signal) A1. And, when the pulse "1" of Send signal (data transfer request signal) S1 is inputted into the handshake transfer control circuit 811 controlling the parallel data latch 821 with the input data to the latch defined, the data is latched in the parallel data latch 821 and outputted into the combinational logic circuit 831. Then, data is processed by the combinational logic circuit 831 to define the input data to the parallel data latch 822, and when Ack signal A2 from the handshake transfer control circuit 812 is inputted into the handshake transfer control circuit 811, the handshake transfer control circuit 811 sends the pulse "1" of Send signal S2 to the handshake transfer control circuit 812. Thereafter, in similar manner, the data pulse of Send signal is propagated sequentially as S1, S2, S3 and S4 through the handshake transfer control circuits 811, 812 and 813 according to the return of Ack signal. Following the pulse propagation, the open/close operation of the parallel data latches 821, 822 and 823 is sequentially controlled, causing the input data to be transferred sequentially between the parallel data latches 821, 822 and 823.
Now, the input data is assumed to consist of a pair of an operation code portion indicating the kind of operation and a data portion being the object of operation. Of the input data, the operation code portion is decoded at the decode unit of the combinational logic circuit 831 (832). According to that result, the processing content for the data portion, such as addition or subtraction, is determined to be processed at the logic unit.
Thus, with the input data passed through the pipeline processing apparatus, various complex processing can be executed as a whole.
However, in each stage of pipeline processing, in the case where the next stage is occupied with the preceding data, that is, the data is stagnated, the following data is stopped at the stage previous to the next stage. For example, in the case where the preceding data is stagnated at the stage between the parallel data latches 822 and 823, the Ack signal A3 from the handshake transfer control circuit control circuit 813 is converted to "1" in order to transfer the following data from the parallel data latch 822 to the latch 823, with the result that Send signal S3 sent from the handshake transfer control circuit 812 to the circuit 813 is kept at the state holding "1". This causes the following data to be sequentially stopped thereafter.
Even when the data transfer is stopped as above, the data is required to be positively held at each parallel data latch 821, 822 and 823, so that the circuit for 1 bit of each parallel data latch 821, 822 and 823 consists of the static latch as shown in FIG. 2 with the reference symbol 11 (12). However, FIG. 2 shows a simple data transfer apparatus omitting the combinational logic circuit which executes data processing.
In FIG. 2, the reference numerals 11 and 12 are logic circuit diagrams each of which shows a data latch circuit having 40-bits width (equivalent to the 821, 822 or 823 in FIG. 1), with 40 sets of a latch circuit 110 (120) for 1 bit being located in parallel. The latch circuit 110 (120) consists of inverter buffers 111, 112 and 113 (121, 122 and 123) and transfer gates 114 and 115 (124 and 125).
The reference numerals 13 and 14 are the handshake transfer control circuits (equivalent to the 811, 812 or 813 in FIG. 1) of the above mentioned data latch circuits 11 and 23 respectively, each of which consists of an R-S flip-flop 15 (17) as the first memory means, an R-S flip-flop 16 (18) as the second memory means, a 4-input NAND gate 131 (141) as a data transfer request signal receiving circuit, inverter buffers 134, 135 and 139 (144, 145 and 149) and a 2-input NAND gate 138 (148).
In addition, the first R-S flip-flop 15 (17) consists of 2-input NAND gates 132 and 133 (142 and 143), and the second R-S flip-flop 16 (18) consists of 2-input NAND gates 136 and 137 (146 and 147).
More specifically, the pulse S1 (S2) of Send signal (data transfer request signal) from the proceeding stage is sent to the one input of the 4-input NAND gate 131 (141) in the control circuit 13 (14), and the output of the 4-input NAND gate 131 (141) is connected to the set terminal S of the first R-S flip-flop 15 (17). And, the reset terminal R of the first R-S flip-flop 15 (17) receives an acknowledge signal A2 (A3) from the control circuit in the next stage. The acknowledge signal A2 (A3) is also sent to the one input of the 4-input NAND gate 131 (141).
The signal from the output terminal Q of the R-S flip-flop 15 (17) is sent as the inversion signal S2 (S3) of Send signal pulse S2 (S3) through the inverter buffer 134 (144) to the transfer gate 114 (124) in the data latch circuit 1 (12), and to the one input of the 4-input NAND gate 141 in the control circuit 14 of the next stage. And, the signal from the inversion output terminal Q of the second R-S flip-flop 16 (18) is sent through the inverter buffer 135 (145) to the transfer gate 115 (125) in the data latch circuit 11 (12), and to the one input of its own 4-input NAND gate 131 (141).
Send signal pulse S1 (S2) from the preceding stage is also sent to the reset terminal R of the second R-S flip-flop 16 (18), and the output of the 4-input NAND gate 131 (141) is also sent to the set terminal S of the second R-S flip-flop 16 (18). And, the signal from the inversion output terminal Q of the second R-S flip-flop 16 (18) is sent to one input of the NAND gate 138 (148) whose other input receives a reset signal RESET. The output of the NAND gate 138 (148) is sent as an acknowledge signal A1 (A2) through the inverter buffer 139 (149) to the preceding stage and to the last one input of its own 4-input NAND gate 131 (141).
Actual configuration of a data transfer circuit is such that plural combinations of such data latch circuit 11 (12) and control circuit 13 (14) are connected in cascade.
A conventional transfer circuit having a configuration mentioned above is operated as follows:
When in an initial state the reset signal RESET converts to "1", entire signal lines are directly initialized.
When Send signal pulse S1 is inputted into the data transfer control circuit 13, the data transfer control circuit makes the flip-flop 15 consisting of NAND gates 132 and 133 to set state. This causes Send signal S2 to be converted to "1" and its inversion output S2 to be converted to "0", so that the data latch circuit 11 controlled by the data transfer control circuit 13 is made to latch state (input change forbidden state) to define the latch output. At the same time, Send signal S2 to the data transfer control circuit 14 in the next stage converts to active state "1", so that all four inputs of the 4-input NAND gate 141 in the next stage convert to "1". This causes both the R-S flip-flop 17 consisting of NAND gates 142 and 143 and the R-S flip-flop 18 consisting of NAND gates 146 and 147 to be set, and the acknowledge signal A2 converts to non-active state "0".
The change of the acknowledge signal A2 to active state causes the flip-flop 15 in the data transfer control circuit 13 to be reset, and Send signal S2 converts to non-active state "0".
At this point, even if Send signal S1 is still active state "1", the flip-flop 16 still holds set state so that the output of the inverter 139 is "0" and all inputs of the 4-input NAND gate 131 are not "1". Therefore, the flip-flop 15 is not set once again, so that no extra Send signal S2 is generated.
Thereafter, once Send signal S1 converts to non-active state "0", at that point the flip-flop 16 is reset, and the output of the inverter 139 converts to "1". Therefore, when, at this point or thereafter, Send signal S1 converts to active state once again, all inputs of the 4-input NAND gate 131 convert to "1", causing the flip-flops 15 and 16 to be set and new Send signal pulse S2 to be generated.
The series of operation mentioned above is shown in FIG. 3 of timing chart.
Referring to FIG. 3, it will be seen that, at the time u, H1 and A2 among inputs S1, H1, A1 and A2 of the 4-input NAND gate 131 return to "1", but A1 keeps "0", so that the generation of a new M1 pulse is suppressed.
The signal A1 returns to "1" in response to the change of Send signal S1 to non-active state "0", so that, at the time v when Send signal pulse S1 corresponding to WORD 2 is inputted, all inputs S1, H1, A1 and A2 of the 4-input NAND gate go to "1". Therefore, a normal M2 pulse in response to WORD 2 is generated.
As apparent by the above description, referring to FIG. 2, at the time when the handshake transfer control circuit 13 receives Send Signal S1 and generates Send signal S2 to the next stage, the circuit turns off the transfer gate 114 and on the transfer gate 115, keeping the input data value at the node N1 in the latch circuit 110. Since the above mentioned state is kept while Send signal S2 keeps "1", the latch circuit consisting of the inventors 112 and 113 is operated to hold the signal level of the node N1 static state.
On the other hand, in response to the receiving of Ack signal A2 from the next stage, the level of Send signal S converts to "0", so that the transfer gate 114 is turned on and the transfer gate 115 is off. This caused the condition of the path from input to output side in the date latch circuit to become transparent, making the acceptance of succeeding data possible.
Now, conventional data transfer apparatus as mentioned above requires the charge and discharge of the gate electrode in the transfer gates 114 (124) and 115 (125) for each pass of one data. Therefore, such a problem occurs that the wider the bit of the data to be transferred the larger the power consumption, together with increased calorific value.